In recent years, there has been a rapid progress in the downsizing, thinning and densification of electronic apparatus, such as portable devices. In addition, the number of terminals has been increased due to speeding up and functional upgrading of semiconductor devices. Consequently, there is a demand for the thinning, miniaturization and densification of packages equipped with semiconductor chips.
Conventionally, a substrate including through-holes, such as a build-up substrate, has been generally known as a wiring substrate. It is difficult to thin, miniaturize and densify the substrate, however, since the substrate is thick and the through-hole pitch thereof is large. In addition, the presence of through-holes makes the substrate unsuitable for high-speed signal transmission.
Although a thin substrate, such as a tape substrate, is also used concurrently, the substrate is limited to a single or two interconnect layers due to the manufacturing method of the substrate. In addition, the base material of a tape expands and contracts significantly, and hence the positional accuracy of patterns is inferior to that of a build-up substrate. Thus, it is difficult to densify the tape substrate.
When mounting semiconductor chips, flip-chip interconnection using solder balls, wire-bonding interconnection using gold wires, or the like is used. It is difficult, however, to narrow a pitch in either case of these interconnection methods.
In the flip-chip interconnection, a semiconductor chip and a wiring substrate are interconnected through bumps formed using microscopic solder balls or the like. However, as the number of terminals of the semiconductor chip increases or the pitch thereof becomes narrower, it is increasingly difficult to achieve bump-based interconnection. In addition, since the strength of the bumps themselves decreases, connection points are liable to break down. Furthermore, an electric resistance value increases at a connecting part. Consequently, voids due to the migration of metal atoms dependent on an electric current direction tend to occur and, therefore, a connection failure is likely to occur.
In the wire bonding interconnection, a wire, as typified by a gold wire, becomes liable to break if the diameter thereof is decreased in order to narrow a pitch. In addition, the margin of connection conditions decreases, thus making it difficult to achieve stable interconnection.
As an example of the above-described flip-chip interconnection, patent document 1 (Japanese Patent Laid-Open No. 2001-185653) discloses a semiconductor device in which a frame having an opening in the center thereof and made of metal or the like is provided on a multilayer organic insulated substrate including an interconnect layer and a via, and a semiconductor chip is mounted in the opening using bumps. In addition, patent document 2 (Japanese Patent Laid-Open No. 2001-144245) discloses a semiconductor package in which a frame-like metal plate having an opening is provided on a multilayer resin wiring substrate and a semiconductor chip is mounted in the opening using bumps.
As a packaging technique capable of densification, there has been recently proposed a technique of forming a multilayer interconnect structure directly onto a semiconductor chip according to a design rule adapted to the connection pitch of the semiconductor chip.
Patent document 3 (Japanese Patent Laid-Open No. 2002-16173) discloses a semiconductor device including a substrate having a concave portion and composed of a bottom plate and a resin frame material, a semiconductor chip mounted within this concave portion, and a multilayer interconnect structure including an organic insulating layer, a metal via and an interconnect layer and provided so as to cover this semiconductor chip and a surface of the substrate.
Patent document 4 (Japanese Patent Laid-Open No. 2002-246506) discloses a multilayer printed-wiring board including a resin substrate having a concave portion, an IC chip mounted within this concave portion, and a multilayer interconnect structure provided so as to cover this IC chip and a surface of the substrate. The patent document also discloses a multilayer printed-wiring board in which a substrate is composed of a plate-like heat sink and a resin layer having a penetrating opening, an IC chip is mounted in the opening of this substrate, and a multilayer interconnect structure is provided thereon.
Patent document 5 (Japanese Patent Laid-Open No. 2004-335641) discloses a method for manufacturing a substrate containing semiconductor elements, including: bonding a semiconductor chip to a first sheet; preparing a second sheet having an opening and composed of a insulating resin and placing the second sheet so that the semiconductor chip is housed in the opening; laminating a third sheet composed of a resin layer and a conductive layer with the resin layer positioned underneath the conductive layer; collectively thermocompression-bonding the first, second and third sheets; electrically connecting the electrode portion of the semiconductor chip and the conductive layer of third sheet to each other; and pattern-processing the conductive layer of the third sheet to form an interconnect.
Patent document 6 (Japanese Patent Laid-Open No. 2005-311249) discloses a parts-containing multilayer substrate including: a core layer in which a metal layer is laminated through a resin layer and openings having different heights are formed; electronic components mounted within the openings of this core layer; and an interconnect structure formed on both surfaces of the core layer.